(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method that provides enhanced adhesion strength between layers of mold resin and adjacent layers of polyimide.
(2) Description of the Prior Art
For the creation of conventional semiconductor devices, the surface of the completed device is typically covered with a relatively thick layer of passivation to protect this surface against such detrimental impacts as mechanical damage and scratching or foreign particles accumulating on or otherwise affecting the surface of the semiconductor device. A protective layer may furthermore be used to protect the completed semiconductor device against mechanical or thermal stress that may be introduced during and as a consequence of additional packaging operations of the device. As a consequence, a protective layer that is created over the surface of a completed semiconductor device must be resistant to thermal and mechanical stress, the layer must not be affected by chemical substances that may come into contact with the surface of the protective layer, the layer must have good adhesion to the surface over which the protective layer is deposited, the layer must be impervious to the penetration of moisture, must provide good electrical isolation and must be thermally matched with adjacent layers in order to accommodate different Coefficients of Thermal Expansion (CTE) of these layers.
The protective coating that is deposited over the surface of a completed semiconductor device must in many of the applications of the protective layer be penetrated in order to provide electrical and functional access to the protected semiconductor device. Contact pads to the protected device are for this purpose provided over an exposed surface of the device. The contact pads typically serve as an interface between the semiconductor device and conductive traces that further interconnect the device, frequently by means of complex and overlying layers of interconnect metal that are separated by layers of dielectric, to surrounding electrical circuitry of electrical components. For this reason, the protective layer must also support a technique, which is preferably a technique that is additionally used for other applications that are used for the creation of semiconductor device, for patterning and etching the protective layer for the creation of openings through the protective layer.
It is further required that the deposition of a protective layer provides the additional benefit of creating a surface of good planarity, even in applications where the surface over which the layer of passivation is deposited has relatively poor planarity so that the layer of passivation contributes to improving the overall planarity of the created structure. This leads to the requirement that the material that is used for the protective layer must be of a relatively viscous nature so that voids or surface irregularities in the surface over which the protective layer is deposited are filled, providing an improved surface planarity for the completed protective layer.
Of the above highlighted requirements for a layer of material that is used as a protective layer over the surface of a completed semiconductor device, the invention concentrates on potential problems that are encountered by mismatches between the Coefficients of Thermal Expansion (CTE) of adjacent and overlying layers of the package. The stresses that are introduced by CTE mismatch have long been known as leading to significant mechanical damage to the completed package such as cracking of the die supporting layer or cracking of the thereon mounted semiconductor die. Conventionally, to reduce the effect of CTE mismatch, a coating of polyimide is first deposited over the surface that is to be protected after which the protective layer is formed over the surface of the layer of polyimide.
One of the frequently applied materials for the formation of a protective layer is mold resin. It is however known in the art that there is a relatively large mismatch between the CTE of polyimide and mold resin. The invention addresses this concern by providing a new method of interfacing the deposited layer of polyimide to the thereover created layer of mold resin.
U.S. Pat. No. 5,937,279 (Sawada et al.) shows a packaging process to reduce cracks due to stress.
U.S. Pat. No. 5,883,001 (Jin et al.) shows a process to improve CU pad adhesion.
U.S. Pat. No. 5,940,277 (Farnworth et al.) and U.S. Pat. No. 5,883,001 (Jin et al.) are related patents.